Expand description
LiteX register abstraction types
LiteX is able to generate vastly different SoC with different buswidths, CSR widths and configurations
This module defines interfaces very similar to tock_registers
(and based on tock_registers) for various register- and
bus-width configurations
Essentially, the bus data width (default 32 bit), the CSR data width, the CSR byte ordering and naturally the desired register width can change. This module defines generic traits for accessing registers and register abstraction structs.
The different register types of a specific SoC configuration are
combined using a
LiteXSoCRegisterConfiguration
structure, which can be used to adapt the register interfaces of
peripherals to the different configurations.
§Naming Scheme
The generated register abstractions follow the naming scheme
<AccessTypes><RegisterWidth>C<CSRDataWidth>B<BaseWidth>where AccessType in { ReadOnly, WriteOnly, ReadWrite },
RegisterWidth in { 8, 16, 32, 64 }, CSRDataWidth in { 8, 32 }, BaseWidth in { 32 }.
Macros§
- Define register types and fields.
Structs§
- Workaround-wrapper for readable LiteX registers
- Workaround-wrapper for read- and writable LiteX registers
- Workaround-wrapper for writable LiteX registers
Enums§
- Collection of LiteX register abstraction types
- Collection of LiteX register abstraction types
Traits§
- Trait to be implemented by custom register structs that support reading the current value
- Trait to be implemented by custom register structs that support writing to them
- Register abstraction types collection
- Readable register
- Readable and writable register
- Extension of the
tock_registersUIntLiketrait. - Writeable register