Module top_earlgrey

This file contains enums and consts for use within the Rust codebase.

These definitions are for information that depends on the top-specific chip configuration, which includes:

• Device Memory Information (for Peripherals and Memory)
• PLIC Interrupt ID Names and Source Mappings
• Alert ID Names and Source Mappings
• Pinmux Pin/Select Names
• Power Manager Wakeups

Enums

• AlertId
  Alert Handler Alert Source.
• AlertPeripheral
  Alert Handler Source Peripheral.
• DirectPads
  Dedicated Pad Selects
• GateableClocks
  Clock Manager Software-Controlled (“Gated”) Clocks.
• HintableClocks
  Clock Manager Software-Hinted Clocks.
• MuxedPads
  Muxed Pad Selects
• PinmuxInsel
  Pinmux MIO Input Selector.
• PinmuxMioOut
  Pinmux MIO Output.
• PinmuxOutsel
  Pinmux Peripheral Output Selector.
• PinmuxPeripheralIn
  Pinmux Peripheral Input.
• PlicIrqId
  PLIC Interrupt Source.
• PlicPeripheral
  PLIC Interrupt Source Peripheral.
• PlicTarget
  PLIC Interrupt Target.
• PowerManagerResetRequests
  Power Manager Reset Request Signals
• PowerManagerWakeUps
  Power Manager Wakeup Signals
• ResetManagerSwResets
  Reset Manager Software Controlled Resets

Constants

• ADC_CTRL_AON_BASE_ADDR
  Peripheral base address for adc_ctrl_aon in top earlgrey.
• ADC_CTRL_AON_SIZE_BYTES
  Peripheral size for adc_ctrl_aon in top earlgrey.
• AES_BASE_ADDR
  Peripheral base address for aes in top earlgrey.
• AES_SIZE_BYTES
  Peripheral size for aes in top earlgrey.
• ALERT_FOR_PERIPHERAL
  Alert Handler Alert Source to Peripheral Map
• ALERT_HANDLER_BASE_ADDR
  Peripheral base address for alert_handler in top earlgrey.
• ALERT_HANDLER_SIZE_BYTES
  Peripheral size for alert_handler in top earlgrey.
• AON_TIMER_AON_BASE_ADDR
  Peripheral base address for aon_timer_aon in top earlgrey.
• AON_TIMER_AON_SIZE_BYTES
  Peripheral size for aon_timer_aon in top earlgrey.
• AST_BASE_ADDR
  Peripheral base address for ast in top earlgrey.
• AST_SIZE_BYTES
  Peripheral size for ast in top earlgrey.
• CLKMGR_AON_BASE_ADDR
  Peripheral base address for clkmgr_aon in top earlgrey.
• CLKMGR_AON_SIZE_BYTES
  Peripheral size for clkmgr_aon in top earlgrey.
• CSRNG_BASE_ADDR
  Peripheral base address for csrng in top earlgrey.
• CSRNG_SIZE_BYTES
  Peripheral size for csrng in top earlgrey.
• EDN0_BASE_ADDR
  Peripheral base address for edn0 in top earlgrey.
• EDN0_SIZE_BYTES
  Peripheral size for edn0 in top earlgrey.
• EDN1_BASE_ADDR
  Peripheral base address for edn1 in top earlgrey.
• EDN1_SIZE_BYTES
  Peripheral size for edn1 in top earlgrey.
• EFLASH_BASE_ADDR
  Memory base address for eflash in top earlgrey.
• EFLASH_SIZE_BYTES
  Memory size for eflash in top earlgrey.
• ENTROPY_SRC_BASE_ADDR
  Peripheral base address for entropy_src in top earlgrey.
• ENTROPY_SRC_SIZE_BYTES
  Peripheral size for entropy_src in top earlgrey.
• FLASH_CTRL_CORE_BASE_ADDR
  Peripheral base address for core device on flash_ctrl in top earlgrey.
• FLASH_CTRL_CORE_SIZE_BYTES
  Peripheral size for core device on flash_ctrl in top earlgrey.
• FLASH_CTRL_MEM_BASE_ADDR
  Peripheral base address for mem device on flash_ctrl in top earlgrey.
• FLASH_CTRL_MEM_SIZE_BYTES
  Peripheral size for mem device on flash_ctrl in top earlgrey.
• FLASH_CTRL_PRIM_BASE_ADDR
  Peripheral base address for prim device on flash_ctrl in top earlgrey.
• FLASH_CTRL_PRIM_SIZE_BYTES
  Peripheral size for prim device on flash_ctrl in top earlgrey.
• GPIO_BASE_ADDR
  Peripheral base address for gpio in top earlgrey.
• GPIO_SIZE_BYTES
  Peripheral size for gpio in top earlgrey.
• HMAC_BASE_ADDR
  Peripheral base address for hmac in top earlgrey.
• HMAC_SIZE_BYTES
  Peripheral size for hmac in top earlgrey.
• I2C0_BASE_ADDR
  Peripheral base address for i2c0 in top earlgrey.
• I2C0_SIZE_BYTES
  Peripheral size for i2c0 in top earlgrey.
• I2C1_BASE_ADDR
  Peripheral base address for i2c1 in top earlgrey.
• I2C1_SIZE_BYTES
  Peripheral size for i2c1 in top earlgrey.
• I2C2_BASE_ADDR
  Peripheral base address for i2c2 in top earlgrey.
• I2C2_SIZE_BYTES
  Peripheral size for i2c2 in top earlgrey.
• KEYMGR_BASE_ADDR
  Peripheral base address for keymgr in top earlgrey.
• KEYMGR_SIZE_BYTES
  Peripheral size for keymgr in top earlgrey.
• KMAC_BASE_ADDR
  Peripheral base address for kmac in top earlgrey.
• KMAC_SIZE_BYTES
  Peripheral size for kmac in top earlgrey.
• LC_CTRL_BASE_ADDR
  Peripheral base address for lc_ctrl in top earlgrey.
• LC_CTRL_SIZE_BYTES
  Peripheral size for lc_ctrl in top earlgrey.
• MMIO_BASE_ADDR
  MMIO Region
• MMIO_SIZE_BYTES
• NUM_DIO_PADS
• NUM_MIO_PADS
• OTBN_BASE_ADDR
  Peripheral base address for otbn in top earlgrey.
• OTBN_SIZE_BYTES
  Peripheral size for otbn in top earlgrey.
• OTP_CTRL_CORE_BASE_ADDR
  Peripheral base address for core device on otp_ctrl in top earlgrey.
• OTP_CTRL_CORE_SIZE_BYTES
  Peripheral size for core device on otp_ctrl in top earlgrey.
• OTP_CTRL_PRIM_BASE_ADDR
  Peripheral base address for prim device on otp_ctrl in top earlgrey.
• OTP_CTRL_PRIM_SIZE_BYTES
  Peripheral size for prim device on otp_ctrl in top earlgrey.
• PATTGEN_BASE_ADDR
  Peripheral base address for pattgen in top earlgrey.
• PATTGEN_SIZE_BYTES
  Peripheral size for pattgen in top earlgrey.
• PINMUX_AON_BASE_ADDR
  Peripheral base address for pinmux_aon in top earlgrey.
• PINMUX_AON_SIZE_BYTES
  Peripheral size for pinmux_aon in top earlgrey.
• PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET
• PINMUX_PERIPH_OUTSEL_IDX_OFFSET
• PLIC_INTERRUPT_FOR_PERIPHERAL
  PLIC Interrupt Source to Peripheral Map
• PWM_AON_BASE_ADDR
  Peripheral base address for pwm_aon in top earlgrey.
• PWM_AON_SIZE_BYTES
  Peripheral size for pwm_aon in top earlgrey.
• PWRMGR_AON_BASE_ADDR
  Peripheral base address for pwrmgr_aon in top earlgrey.
• PWRMGR_AON_SIZE_BYTES
  Peripheral size for pwrmgr_aon in top earlgrey.
• RAM_MAIN_BASE_ADDR
  Memory base address for ram_main in top earlgrey.
• RAM_MAIN_SIZE_BYTES
  Memory size for ram_main in top earlgrey.
• RAM_RET_AON_BASE_ADDR
  Memory base address for ram_ret_aon in top earlgrey.
• RAM_RET_AON_SIZE_BYTES
  Memory size for ram_ret_aon in top earlgrey.
• ROM_BASE_ADDR
  Memory base address for rom in top earlgrey.
• ROM_CTRL_REGS_BASE_ADDR
  Peripheral base address for regs device on rom_ctrl in top earlgrey.
• ROM_CTRL_REGS_SIZE_BYTES
  Peripheral size for regs device on rom_ctrl in top earlgrey.
• ROM_CTRL_ROM_BASE_ADDR
  Peripheral base address for rom device on rom_ctrl in top earlgrey.
• ROM_CTRL_ROM_SIZE_BYTES
  Peripheral size for rom device on rom_ctrl in top earlgrey.
• ROM_SIZE_BYTES
  Memory size for rom in top earlgrey.
• RSTMGR_AON_BASE_ADDR
  Peripheral base address for rstmgr_aon in top earlgrey.
• RSTMGR_AON_SIZE_BYTES
  Peripheral size for rstmgr_aon in top earlgrey.
• RV_CORE_IBEX_CFG_BASE_ADDR
  Peripheral base address for cfg device on rv_core_ibex in top earlgrey.
• RV_CORE_IBEX_CFG_SIZE_BYTES
  Peripheral size for cfg device on rv_core_ibex in top earlgrey.
• RV_DM_MEM_BASE_ADDR
  Peripheral base address for mem device on rv_dm in top earlgrey.
• RV_DM_MEM_SIZE_BYTES
  Peripheral size for mem device on rv_dm in top earlgrey.
• RV_DM_REGS_BASE_ADDR
  Peripheral base address for regs device on rv_dm in top earlgrey.
• RV_DM_REGS_SIZE_BYTES
  Peripheral size for regs device on rv_dm in top earlgrey.
• RV_PLIC_BASE_ADDR
  Peripheral base address for rv_plic in top earlgrey.
• RV_PLIC_SIZE_BYTES
  Peripheral size for rv_plic in top earlgrey.
• RV_TIMER_BASE_ADDR
  Peripheral base address for rv_timer in top earlgrey.
• RV_TIMER_SIZE_BYTES
  Peripheral size for rv_timer in top earlgrey.
• SENSOR_CTRL_BASE_ADDR
  Peripheral base address for sensor_ctrl in top earlgrey.
• SENSOR_CTRL_SIZE_BYTES
  Peripheral size for sensor_ctrl in top earlgrey.
• SPI_DEVICE_BASE_ADDR
  Peripheral base address for spi_device in top earlgrey.
• SPI_DEVICE_SIZE_BYTES
  Peripheral size for spi_device in top earlgrey.
• SPI_HOST0_BASE_ADDR
  Peripheral base address for spi_host0 in top earlgrey.
• SPI_HOST0_SIZE_BYTES
  Peripheral size for spi_host0 in top earlgrey.
• SPI_HOST1_BASE_ADDR
  Peripheral base address for spi_host1 in top earlgrey.
• SPI_HOST1_SIZE_BYTES
  Peripheral size for spi_host1 in top earlgrey.
• SRAM_CTRL_MAIN_RAM_BASE_ADDR
  Peripheral base address for ram device on sram_ctrl_main in top earlgrey.
• SRAM_CTRL_MAIN_RAM_SIZE_BYTES
  Peripheral size for ram device on sram_ctrl_main in top earlgrey.
• SRAM_CTRL_MAIN_REGS_BASE_ADDR
  Peripheral base address for regs device on sram_ctrl_main in top earlgrey.
• SRAM_CTRL_MAIN_REGS_SIZE_BYTES
  Peripheral size for regs device on sram_ctrl_main in top earlgrey.
• SRAM_CTRL_RET_AON_RAM_BASE_ADDR
  Peripheral base address for ram device on sram_ctrl_ret_aon in top earlgrey.
• SRAM_CTRL_RET_AON_RAM_SIZE_BYTES
  Peripheral size for ram device on sram_ctrl_ret_aon in top earlgrey.
• SRAM_CTRL_RET_AON_REGS_BASE_ADDR
  Peripheral base address for regs device on sram_ctrl_ret_aon in top earlgrey.
• SRAM_CTRL_RET_AON_REGS_SIZE_BYTES
  Peripheral size for regs device on sram_ctrl_ret_aon in top earlgrey.
• SYSRST_CTRL_AON_BASE_ADDR
  Peripheral base address for sysrst_ctrl_aon in top earlgrey.
• SYSRST_CTRL_AON_SIZE_BYTES
  Peripheral size for sysrst_ctrl_aon in top earlgrey.
• UART0_BASE_ADDR
  Peripheral base address for uart0 in top earlgrey.
• UART0_SIZE_BYTES
  Peripheral size for uart0 in top earlgrey.
• UART1_BASE_ADDR
  Peripheral base address for uart1 in top earlgrey.
• UART1_SIZE_BYTES
  Peripheral size for uart1 in top earlgrey.
• UART2_BASE_ADDR
  Peripheral base address for uart2 in top earlgrey.
• UART2_SIZE_BYTES
  Peripheral size for uart2 in top earlgrey.
• UART3_BASE_ADDR
  Peripheral base address for uart3 in top earlgrey.
• UART3_SIZE_BYTES
  Peripheral size for uart3 in top earlgrey.
• USBDEV_BASE_ADDR
  Peripheral base address for usbdev in top earlgrey.
• USBDEV_SIZE_BYTES
  Peripheral size for usbdev in top earlgrey.